1. Field of the Invention
The embodiments of the invention generally relate to semiconductor wafers, and, more particularly, to semiconductor wafer structures and methods of forming the structures that balance variations in reflectance and absorption characteristics.
2. Description of the Related Art
The fabrication of a semiconductor wafer typically involves the use of a rapid thermal anneal (RTA) process to affect the electrical properties of active devices on the wafer. Specifically, this RTA process can be used to activate dopants, diffuse dopants, re-amporphize structures, repair damage from ion implantation processes, etc. RTAs are typically performed by powerful halogen lamp-based heating equipment which directs radiation onto a wafer surface, thereby, allowing fast changes in the temperature of the wafer. However, variations in the reflectance and absorption in different regions of the wafer can result in non-uniform temperature changes across the wafer (e.g., varying the 10° C. or more).
Variations in reflectance and absorption characteristics can be caused by different factors, such as different materials and/or different thicknesses of materials in different regions of the wafer. These non-uniform temperature changes can vary dopant activation, damage repair, etc. across the wafer and can, thereby, cause variations in threshold voltages, sheet resistances, drive currents, leakage currents, etc. Thus, non-uniform temperature changes can cause significant, location-dependent, variations in device performance.
Recently-developed complementary metal oxide semiconductor (CMOS) devices have incorporated epitaxially grown silicon germanium (eSiGe) into the source/drain regions of the p-type field effect transistors in order to enhance performance. Thus, these devices comprise both pfets with silicon germanium and n-type field effect transistors (nfets) with single crystalline silicon. However, the reflectance and absorption characteristics of silicon germanium and single crystalline silicon are different and can cause performance dispersion. Specifically, the reflectivity of eSiGe can be up to 10% higher than that of single crystalline silicon, thereby, causing a performance dispersion of up to 20%.
Similarly, hybrid orientation (HOT) wafers have been developed which silicon on insulator (SOI) sections having one orientation (e.g., 110) to enhance the performance of one type of field effect transistors (e.g., pfets) and bulk silicon sections having a different orientation (e.g., 100) to enhance the performance of another type of field effect transistor (e.g., nfets). However, because of their different thicknesses, the SOI and bulk silicon sections have different reflectance characteristics. Specifically, the reflectivity of the SOI sections can be up to 15% higher than the bulk silicon sections, thereby, causing a performance dispersion of up to 30%.
Furthermore, as technologies continue to scale, anneal ramp times will continue to decrease (e.g., to sub-second ramps) and these faster ramp times will be accompanied by an even greater sensitivity to variations in reflectance and absorption characteristics across a wafer.